Gabatarwa zuwa PCIe 5.0 ƙayyadaddun bayanai

• Gabatarwa zuwa PCIe 5.0 ƙayyadaddun bayanai

An kammala ƙayyadaddun ƙayyadaddun PCIe 4.0 a cikin 2017, amma dandamalin mabukaci ba su goyi bayan sa ba har sai jerin AMD's 7nm Rydragon 3000, kuma a baya samfuran kawai kamar supercomputing, babban ma'ajiyar manyan kamfanoni, da na'urorin cibiyar sadarwa sun yi amfani da fasahar PCIe 4.0.Kodayake ba a yi amfani da fasahar PCIe 4.0 akan babban sikeli ba, ƙungiyar PCI-SIG ta daɗe tana haɓaka PCIe 5.0 mai sauri, ƙimar siginar ta ninka daga 16GT/s na yanzu zuwa 32GT/s, bandwidth na iya kaiwa 128GB/ s, kuma an kammala sigar 0.9/1.0.v0.7 na daidaitaccen rubutu na PCIe 6.0 an aika zuwa ga mambobi, kuma ci gaban mizanin yana kan hanya.An ƙara ƙimar fil na PCIe 6.0 zuwa 64 GT/s, wanda shine sau 8 na PCIe 3.0, kuma bandwidth a cikin tashoshi x16 na iya girma fiye da 256GB/s.A wasu kalmomi, saurin PCIe 3.0 x8 na yanzu yana buƙatar tashar PCIe 6.0 ɗaya kawai don cimma.Dangane da abin da ya shafi v0.7, PCIe 6.0 ya cimma mafi yawan abubuwan da aka sanar da farko, amma amfani da wutar lantarki har yanzu yana ƙara ingantawa.d, kuma ma'auni ya ƙaddamar da sabbin kayan daidaita wutar lantarki na L0p.Tabbas, bayan sanarwar a cikin 2021, PCIe 6.0 na iya kasancewa ta kasuwanci a cikin 2023 ko 2024 a farkon.Misali, an amince da PCIe 5.0 a cikin 2019, kuma yanzu ne kawai akwai lokuta na aikace-aikacen.

Idan aka kwatanta da ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun bayanai na baya, ƙayyadaddun PCIe 4.0 sun zo da ɗan lokaci kaɗan.An gabatar da ƙayyadaddun PCIe 3.0 a cikin 2010, shekaru 7 bayan gabatarwar PCIe 4.0, don haka rayuwar ƙayyadaddun PCIe 4.0 na iya zama gajere.Musamman, wasu dillalai sun fara kera na'urorin Layer na zahiri na PCIe 5.0 PHY.

Ƙungiyar PCI-SIG tana tsammanin ƙa'idodin biyu za su kasance tare na ɗan lokaci, kuma PCIe 5.0 ana amfani da shi don na'urori masu mahimmanci tare da buƙatun kayan aiki masu girma, irin su Gpus don AI, na'urorin sadarwa, da sauransu, wanda ke nufin cewa PCIe 5.0 ne. yuwuwar bayyana a cibiyar bayanai, cibiyar sadarwa, da mahallin HPC.Na'urori masu ƙarancin buƙatun bandwidth, kamar kwamfutoci, na iya amfani da PCIe 4.0.

Don PCIe 5.0, an ƙara ƙimar siginar daga PCIe 4.0's 16GT/s zuwa 32GT/s, har yanzu tana amfani da 128/130 encoding, kuma an ƙara bandwidth x16 daga 64GB/s zuwa 128GB/s.

Bugu da ƙari, ninka girman bandwidth, PCIe 5.0 yana kawo wasu canje-canje, canza ƙirar lantarki don inganta siginar siginar, dacewa da baya tare da PCIe, da sauransu.Bugu da ƙari, an tsara PCIe 5.0 tare da sababbin ka'idoji waɗanda ke rage jinkiri da sigina a kan dogon nisa.

Ƙungiyar PCI-SIG tana tsammanin kammala nau'in 1.0 na ƙayyadaddun ƙayyadaddun bayanai a cikin Q1 a wannan shekara, amma za su iya haɓaka ƙa'idodi, amma ba za su iya sarrafawa ba lokacin da aka gabatar da na'urar tasha zuwa kasuwa, kuma ana sa ran cewa PCIe 5.0 na farko. na'urorin za su fara buɗewa a wannan shekara, kuma ƙarin samfuran za su bayyana a cikin 2020. Duk da haka, buƙatar haɓaka mafi girma ya haifar da daidaitattun jiki don ayyana ƙarni na gaba na PCI Express.Makasudin PCIe 5.0 shine haɓaka saurin daidaitattun a cikin mafi ƙarancin lokaci mai yuwuwa.Don haka, an tsara PCIe 5.0 don kawai ƙara saurin zuwa ma'aunin PCIe 4.0 ba tare da wasu sabbin abubuwa masu mahimmanci ba.

Misali, PCIe 5.0 baya goyan bayan siginar PAM 4 kuma kawai ya haɗa da sabbin abubuwan da ake buƙata don kunna ma'aunin PCIe don tallafawa 32 GT/s a cikin ɗan gajeren lokaci mai yuwuwa.

Kalubalen hardware

Babban ƙalubale a shirya samfur don tallafawa PCI Express 5.0 zai kasance da alaƙa da tsayin tashoshi.Da sauri ƙimar siginar, mafi girman mitar siginar da ake watsa ta cikin allon PC.Iri biyu na lalacewa ta jiki sun iyakance iyakar abin da injiniyoyi zasu iya yada siginar PCIe:

· 1. Attenuation na tashar

· 2. Tunani da ke faruwa a cikin tashar saboda katsewar impedance a cikin fil, haši, ramuka da sauran tsarin.

Ƙididdigar PCIe 5.0 tana amfani da tashoshi tare da -36dB attenuation a 16 GHz.Mitar 16 GHz tana wakiltar mitar Nyquist don sigina na dijital 32 GT/s.Misali, lokacin da siginar PCIe5.0 ta fara, yana iya samun matsakaicin matsakaicin matsakaicin tsayi-zuwa kololuwar 800 mV.Duk da haka, bayan wucewa ta hanyar da aka ba da shawarar -36dB, duk wani kama da ido bude ya ɓace.Ta hanyar yin amfani da daidaitattun tushen watsawa (de-accentuating) da daidaita mai karɓa (haɗin CTLE da DFE) za a iya siginar PCIe5.0 ta hanyar tashar tsarin kuma mai karɓa ya fassara shi daidai.Matsakaicin tsayin ido na siginar PCIe 5.0 shine 10mV (bayan daidaitawa).Ko da tare da madaidaicin ƙarancin jitter na kusa, mahimmancin attenuation na tashar yana rage girman siginar har zuwa inda za a iya rufe duk wani nau'i na lalacewar siginar da ke haifar da tunani da crosstalk don mayar da ido.